The present invention relates in general to semiconductor packaging, and in particular to a low resistance, high current semiconductor package that is particularly well suited for power devices.
Semiconductor power switching devices and particularly power MOSFET devices continue to push the lower limits of on-state resistance. While silicon process technology has advanced significantly in the past decade, essentially the same decades-old package technology continues as the primary packaging means. Epoxy or solder die attach along with aluminum or gold wire interconnects is still the preferred power device package methodology. FIG. 1 illustrates typical package wiring for a power MOSFET 100. Wire bonds 108 connect the device (or die) 100 to the lead frames for source terminal 104 and gate terminal 106. Even if provided in multiple locations (as shown for source connections 108), this type of wire bonding can add relatively large resistance to the otherwise low on-state resistance of the high current MOSFET. In addition, placement of the wires on the metalized surface 110 of the device is constrained, among other factors, by wire length, bond size relative to the bond pad area, and vertical clearance inside the molded body. Even the relatively thick top metalization can add significantly to the resistance and can be compounded by wire interconnect placement limitations.
There is therefore a need for improved packaging techniques that minimize resistance for semiconductor devices such as power MOSFETs.
The present invention provides a low resistance wireless package for semiconductor devices such as power MOSFETs. Broadly, the package according to the present invention includes an array of solder interconnections that provides a direct connection between one conductive surface of the semiconductor device and a lead frame element with leads that exit the molded package body. Resistive wire interconnections between the device and the lead frame are thus eliminated and replaced by relatively low-resistance lead frame elements. Furthermore, the present invention allows the size and shape of the lead frame to be tailored to fit the device and to minimize its electrical and thermal resistance. The distributed solder connections on the top metal reduces its resistance to negligible amounts. The combined effect of metal resistance reduction and wire resistance elimination results in a drastic reduction in the package resistance. In a preferred embodiment, the direct lead frame-to-device solder array connection to one conductive surface (e.g., top side) is combined with a die attach mechanism to connect to the other conductive surface (e.g., bottom side) of the device.
Accordingly, the present invention provides a semiconductor package including a silicon die encapsulated by a protective molding; a plurality of solder balls disposed across and making contact to a conductive layer on a top surface of the die; and a metal lead frame making direct contact to the plurality of solder balls and extending outside the protective molding. In one embodiment, a bottom surface of the die is attached directly to a second metal lead frame through a die attach process, with the second metal lead frame also extending outside the protective molding.
In a specific embodiment, the silicon die comprises a power MOSFET transistor with the top surface metalized and forming a source terminal connecting to the plurality of the solder balls, and the bottom surface forming a drain terminal connecting to the second metal lead frame. Further, a third metal lead frame directly contacts a solder ball connecting to a gate terminal of the MOSFET on the top surface of the die.
In yet another embodiment, the present invention uses a solder ball array mask to create cavities in the passivation layer. the cavities receive the plurality of solder balls and restrict their movement to promote wicking of the solder between the pad surface and the top frame element.
A better understanding of the nature and advantages of the low resistance wireless package of the present invention may be gained with reference to the detailed description and drawings below.